The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, the performance of a chip design is seriously influenced by control of resistance/capacitance (RC), timing, leakage, and topology of the metal/dielectric inter-layers. In semiconductor fabrication, various processing modules are involved. Each module releases some representative information to a design model for follow-up work. Afterward, only a statistical corner can be added onto the simulation model for design reference. Such design flow lacks cross-team interaction, especially when the feature size is dramatically shrunken. Furthermore, in the current IC design flow, patterns used in simulation are too simple than the frequently designed patterns. The existing design method is challenged by various problems. For example, every module in current semiconductor processing modeling, such as lithography patterning, thin film deposition, etching, etc., is independent from other modules. The full chip tape out, as the final design product, cannot be achieved without maximized modeling efficiency. In another problem, the statistical corner is used for design reference and reduces the design flexibility and design margin. Further, if it is desired to use a design layout from a first technology node for fabricating devices of a second technology node, numerous interactions are required between a designer and semiconductor manufacturer.
Therefore, what is needed is a method and a system to provide effective and improved IC design for the advanced IC technologies.